The present invention relates to an inverter i apparatus including at least one arm having first and second power switching devices connected in series between high voltage power source terminals. In particular, the present invention relates to an inverter apparatus having a step-up level shift circuit for transmitting a control signal from a negative side circuit to a positive side circuit and/or a step-down level shift circuit for transmitting a control signal from a positive side circuit to a negative side circuit.
In a conventional inverter apparatus having a first power switching device disposed in a positive side arm (hereafter referred to as upper arm) between high voltage power source terminals and a second power switching device disposed in a negative side arm (hereafter referred to as lower arm) and connected with the first power switching device in a totem-pole form (i.e., in series), the first power switching device of the upper arm is driven in a floating voltage condition with respect to a reference potential and a power source insulated by a transformer is used in a drive circuit for the first power switching device.
For transmitting a drive signal from a negative side circuit to a positive side circuit, a level shift circuit capable of transmitting signals even in the floating voltage condition (hereafter referred to as step-up level shift circuit) is needed. A photocoupler or a pulse transformer is typically used. On the contrary, a level shift circuit for transmitting signals from a positive side circuit to a negative side circuit is hereafter referred to as step-down level shift circuit. Both level shift circuits are required to be high in signal transmission speed and low in power consumption. For achieving a smaller size of an inverter apparatus and a higher speed of signal transmission, it has recently been studied to form the level shift circuit as a monolithic integrated circuit. For example, a step-up level shift circuit has been discussed in IEEE Journal of Solid-State Circuits, Vol. 25, No. 3, Jun. 1990, pp. 677-683.
FIG. 1 is a configuration diagram of a step-up level shift circuit disclosed in the above described literature.
In FIG. 9, Q1 and Q2 denote first and second power switching devices, respectively. Q1 and Q2 belong to an upper arm and a lower arm, respectively. T1 to T10 denote transistors. Among them, T3 and T4 are high voltage N-channel MOSFETs and other transistors are low voltage bipolar transistors. R1 to R6 denote resistors, and N1 to N4 denote logic inverters. Numeral 100 and 101 denote driver circuits for Q1 and Q2, respectively. VE denote a high voltage power source (several hundreds V). Vcc denotes a low voltage power source (15 V). VDD denotes a power source supplying a voltage (7 V) smaller than Vcc. DB and CB denote a diode and a capacitor for forming a low voltage power source for the upper arm, respectively.
The circuit which supplies a set or reset trigger pulse to a flip-flop formed by N1 and N2 is the level shift circuit. A level shift circuit of the set side is formed by a series circuit of R1, T3, T5 and R3 connected between a positive terminal of CB and a negative terminal of Vcc. In the same way, a level shift circuit of the reset side is formed by a series circuit of R2, T4, T7 and R4.
How to drive Q1 by using the level shift circuit configured as described above will hereafter be described. If a set pulse having a pulse width t1 is inputted to an input terminal of a logic inverter N3 and an input terminal of an inverter N4 is fixed at a high level, then the transistors T5 and T6 turn on. Since T5 turns on, gate voltage from VDD is applied between a gate terminal of the MOSFET T3 and a source terminal thereof, thereby turning on T3. As a result, both switch devices T3 and T5 included in the set-side series circuit (R1, T3, T5 and R3) turn on, thereby letting flow a current Is through the series circuit. Since a part of this Is flows as a base current of the transistor T1, the transistor T1 turns on, thereby turning on the transistor T9 as well. Since T9 turns on, a terminal Q of the flip-flop circuit formed by N1 and N2 becomes a low level. As for the state of the flip-flop, Q is hereafter fixed at the low level and Q is fixed at a high level. When a time t1 has elapsed, the set pulse inputted to N3 becomes a high level. However, the flip-flop of N1 and N2 is already fixed in state and does not change. Since the input terminal is fixed at the high level, the output of N4 becomes a low level. Since the transistors T7, T8 and T4 are thus in the off-state, a current does not flow through a reset-side series circuit (R2, T4, T7 and R4). Thereby, T2 and T10 are also in the off-state. Since the output of Q becomes a low level, a driver circuit 100 turns Q1 on. In order to then turn Q1 off, the input terminal of N3 is fixed at the high level and a reset pulse which becomes a low level for an interval t2 is inputted to the input terminal of N4, in contrast with the above described action. Thereby, T10 turns on and the terminal Q of the flip-flop circuit becomes a low level. As for the state of the flip-flop, Q is hereafter fixed at a high level and Q is fixed at a low level. Since Q changes from the low level to the high level, the driver circuit 100 receiving this signal turns Q1 off. At this time, all of the transistors T3, T5 and T6 are in the off-state, and the current Is does not flow through the set-side series circuit.
When the output of Q becomes the low level as a result of application of the set pulse, the driver circuit 100 turns Q1 on by using this signal. At this time, however, the voltage Vo at an output terminal 0 rises abruptly. Noise currents, which are determined by the product of the rate of voltage change dV/dt and drain-source parasitic capacitance of the MOS transistors T3 and T4, flow through T3 and T4. In the illustrated example, influences of the above described noise currents are cancelled by placing T1 and T2 and T9 and T10 in a differential circuit configuration.
By using the differential circuit configuration, the above described level shift circuit is made less susceptible to the influence of the noise currents caused by dV/dt. Achievement of this object makes it a condition that the drain-source parasitic capacitance of T3 is equal to that of T4. On the other hand, if the set pulse is still applied in the low level state when Q1 turns on, T3 is in the on-state and the drain-source parasitic capacitance of T3 in the on-state is different from that of T4 in the off-state. In the above described level shift circuit, therefore, the width t1 of the set pulse and the width t2 of the reset pulse must be made sufficiently short, respectively. If each width is made shorter than the delay time of the circuit, however, a signal can be conveyed to the flip-flop. It is thus not easy to set t1 and t2.
As for the noise currents flowing through T3 and T4 of the above described level shift circuit when Q1 has turned on or turned off, countermeasures have been studied. For the case where the logic state of the terminal Q or Q of the flip-flop is directly inverted by noise, however, countermeasures have not been studied.